Vikram Singh

About

I'm a Staff Research Engineer at Tejas Networks, where I spend most of my days doing intense hands-on work somewhere in the space between research, engineering, and standardization. A good part of that time goes into 3GPP RAN1/RAN2 standardization, where the conversations tend to revolve around integrated sensing and communications (ISAC), sensing assisted communication (SAC), positioning, AI-RAN, RAN digital twin. The less glamorous part, and probably the most useful, is turning ideas into intellectual property that can survive both simulation and standardization and hopefully can be reduced to practice someday.

What time is left, including weekends, tends to go toward work that sits closer to the hardware. I help build and maintain a CUDA-C++/Python platform for large-scale wireless system simulations. That means spending a lot of time thinking about memory movement, arithmetic intensity, GPU throughput, and where performance disappears when it shouldn't. Much of the effort goes into writing optimized CUDA kernels and real-time GPU algorithms for AI-RAN. The goal is simple: make simulations faster, more scalable, and faithful to the systems being modeled. Getting there, as usual, is less simple.

I grew up in a village near Ambala, in North Haryana, in a farming family. I loved the farms, the cattle, and mathematics in roughly equal measure. Most afternoons until sunset went to grazing buffalos and working the fields alongside my family. It was a simple life, and a grounding one. The real turning point was IIT Kanpur, where I completed a master's in Signal Processing and Communications, met some genuinely kind and capable people, and was advised by Prof. Aditya K. Jagannatham. That time and supervision shaped most of what I went on to do.

After IITK I joined Intel's SDG group in Bangalore, but left fairly quickly. The work wasn't what I had hoped for. In October 2018 I joined CEWiT (Centre of Excellence in Wireless Technology), where I found on cutting edge research, development and standardization work related to 5G networks. I contributed to 3GPP standardization on positioning from 2018 through late 2021. I focused on the physical layer and MAC-Scheduler side of 5G, mostly positioning, sidelink, and AI-ML. That meant designing every single positioning algorithm for the 5G physical layer, building and maintaining a system simulator covering 3GPP releases 15 through 18, and developing AI-ML models for channel estimation, symbol demodulation, LDPC decoding, and inter-frequency measurement prediction.

In December 2021 I left CEWiT to start Gigayasa Wireless. The idea was to build a GPU-scalable, 3GPP-compliant simulation tool for 5G/5G-Advanced/6G networks with native AI-in-RAN support, capable of running end-to-end system simulations within an hour. I began by implementing the 38.xxx series standards in Python, line by line, using that to validate the tool against real-world 5G scenarios. By early 2022 I was leading a team, turning that work into production grade software for the ease of usage, deployment and support and integrating AI-ML models for beam prediction, CSI compression and reconstruction, and positioning. We couldn't scale the business to where we had hoped, and eventually wound down.

In August 2024 I joined Tejas Networks, picking up where I had left off: system simulations and 3GPP standardization for 5G-Advanced and 6G.

Outside work

I live in Bengaluru. Outside of work I cook, read, and write occasionally on the blogs page about telecom, AI, quantum communications, GPU scaling, C/C++ CUDA Kernels, system simulation, and the occasional lighthearted take on startups.

Contact

The fastest way to reach me is LinkedIn. I'm also on GitHub and Google Scholar. If email's your preference, send a note to vikram.singh.anttal@gmail.com. My brief technical description can be found in my CV (PDF)

Experience

  1. Tejas Networks

    2024–Present
    • Staff Research Engineer

      2026–Present

      Leading a team driving 3GPP RAN1/RAN2 6G standardization contributions and intellectual property development across emerging wireless technologies. Driving academic collaborations to advance long-term, standards-driven research and algorithm/AI-ML models development for 6G wireless systems. Helped overcome compute resource constraints by optimizing system-level simulation frameworks and leveraging high-performance computing infrastructure to improve simulation scale, efficiency, and turnaround time.

    • Lead Research Engineer

      2024–2026

      Contributed to 3GPP Release 19 5G-Advanced RAN1 standardization activities focused on AI/ML-enabled positioning, beam management, and CSI compression. Authored and filed standards-related patents spanning AI/ML, Integrated Sensing and Communication (ISAC), RAN Digital Twins, and 6G AI/ML use cases for intellectual property development. Led the design and development of a system-level simulation platform used for the evaluation, validation, and performance assessment of 3GPP RAN1 proposals and study items.

  2. Founder and Chief of Technology (CTO)

    Progressed through multiple roles, starting as an individual researcher and developer before taking on increasing leadership responsibilities as the company scaled. At the company's peak, managed a team of 24 members, overseeing technology strategy, product development, cross-functional coordination, product outreach, marketing, and developer experience initiatives.

    • Senior Research Engineer

      2021–2021

      Executed three independent research projects focused on the standardization of Reduced Capability (RedCap) positioning, sidelink positioning, and pre-standardization studies on AI/ML-enabled air-interface enhancements within 3GPP RAN1. Conducted feasibility study and performance evaluations to identify standards impact via system-level simulations, identify opportunities for intellectual property filing.

    • Research Engineer

      2018-2021

      Initiated the 3GPP standardization activities in wireless positioning and authored standards-related patents in the area. Drove the development of a 3GPP-compliant positioning system simulator and led the implementation and evaluation of positioning algorithms aligned with evolving 3GPP specifications.

  3. System on Chip (SoC) Design Engineer

    I was a System on Chip (SoC) Design Engineer in Scalable Performance CPU Development Group (SDG). Responsible for Physical Design and Verification for 3rd Gen Intel Xeon Scalable Processors (Ice Lake).

  4. Masters of Technology in Signal Processing and Communication, Department of Electrical Engineering

    Advisor: Aditya K. Jagannatham.
    Masters Dissertation: "Adaptive Schemes for Spatio-Temporally Correlated Multiuser MIMO Channel Estimation." Developed novel algorithms for multi-user channel estimation and tracking in massive MIMO systems, leveraging temporal and spatial correlation models to improve downlink precoding performance under varying complexity constraints.